The invention relates a delay circuit that delays an input signal and supplies a delay signal having a predetermined phase difference from the input signal.
An analog PLL (Phase Locked Loop) oscillator is utilized for multiplying a clock frequency, a skew adjustment of a clock within an LSI (Large-scale Integrated Circuit), and so on. The analog PLL oscillator is provided as an indispensable circuit (or as a macro of a CAD tool) for actualizing speed-up and scale-up of the LSI over the recent years.
Further, there is a DLL (Delay Locked Loop) circuit as a technology similar to the analog PLL oscillator. The DLL circuit has been in versatile usage with the spread of the fast LSI such as DDR-SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory). The DLL circuit can generate a delay intended by a circuit designer. Therefore, the DLL circuit is an indispensable circuit (or the macro) for generating a desired delay and for interfacing with the fast LSI.
[Patent document 1] Japanese Patent Application Laid-Open Publication No. 2000-163999
[Patent document 2] Japanese Patent Application Laid-Open Publication No. 2001-210020